1. Field of the Invention
This invention relates to multithreaded processors and, more specifically, to a hardware-based method for invalidating obsolete virtual to physical address translations and/or real to physical address translations.
2. Description of the Related Art
Modern computer systems typically include virtual memory space that is shared between multiple processors within a system. Virtual addresses are produced by the processors for each instruction fetch or load or store access to memory. Addresses within the virtual memory space are translated into physical memory addresses, which are used to access physical memory locations. These virtual to physical address translations are typically stored in page tables. In an effort to improve processor performance, a subset of the virtual to physical address translations stored in the page tables may be cached in translation lookaside buffers (TLBs). The TLBs may improve processor performance by decreasing the amount of time required for a processor to determine an actual, physical memory location for an instruction or data. Many TLBs may exist in a multiprocessor computer system, as each processor may include multiple TLBs.
TLBs may be managed entirely by software, or may be managed by a combination of hardware and software techniques. For example, some implementations reload missing TLB entries via a hardware mechanism referred to as hardware table walk. When a virtual address misses in the TLB, the hardware table walk engine searches a set of page tables located in physical memory to find a matching translation. If one is found, hardware updates the TLB; otherwise, hardware signals an exception, and higher-level software resolves the exception. Even in systems that include hardware table walk, software is typically used to manage the TLBs. In particular, when the virtual to physical address maps stored in the page tables change, software is used to remove stale mappings from the TLBs.
A variety of system events may result in changes to the virtual memory space, thus rendering the virtual to physical address translations obsolete. Address maps may change, for example, as a result of migrating virtual pages to disk, terminating processes, allocating virtual memory, or performing disk or network I/O. In response to these events, the page tables storing the obsolete translations may need to be invalidated. Accordingly, the obsolete address translations stored in all of the TLBs in a system may also need to be invalidated, or demapped. The demap process is typically handled by software operations, which require processing of an interrupt for each TLB within each processor in a system. Processing software interrupts to support demapping operations across multiple cores within multiple processors in a system may require significant system overhead, which can result in decreased system performance. As the number of cores within a processor and/or the number of processors within a system increases, the overhead required to process software interrupts for demap operations also increases, particularly for system applications that require frequent changes to the virtual memory space.